1. Field of the Invention
The present invention relates generally to packaging of electronic components. More particularly, the present invention relates to a method of fabricating a wafer level package and the resulting structure.
2. Description of the Related Art
To form a circuit pattern, features in a dielectric layer are filled with plated copper. Typically, this entails formation of the features in the dielectric layer, formation of an electrically conductive seed layer within the features, and filling of the features by plating copper on the electrically conductive seed layer within the features.
Although effective in producing a circuit pattern, the multi-step process is inherently slow and thus has a high associated cost.